In recent years, mobile phones have been remarkably prevailing, and various techniques for reducing cost and increasing the life of batteries have been proposed.
In many of transmitters of mobile phones or the like, a plurality of frequency divider circuits having different division ratios are connected after an oscillator, so that the transmitter can deal with a plurality of frequencies for communications by using one oscillator, thereby reducing the number of oscillators and realizing reduction of the size and the cost of a high-frequency IC.
Of frequency divider circuits used in such transmitters, particularly, a frequency divider circuit used in a process of generating a carrier wave performs an extremely high frequency of switching operation, and the power consumption of such a frequency divider circuit is never small. Therefore, it is desired that the power consumption of the frequency divider circuit is reduced in order to increase the life of a battery.
Examples of conventional frequency divider circuits are an ECL-type frequency divider circuit (see Non-Patent Literature 1, FIG. 2), and a CMOS-inverter-type frequency divider circuit (see Non-Patent Literature 2, FIGS. 6 and 8).
In comparison with the ECL-type frequency divider circuit, in the CMOS-inverter-type frequency divider circuit, phase noise is small even when the CMOS-inverter-type frequency divider circuit is operated at a low voltage, and it is possible to reduce current consumption by configuring the CMOS-inverter-type frequency divider circuit through a CMOS fine process. Therefore, the CMOS-inverter-type frequency divider circuit is advantageous in reduction of power consumption. However, even if the latest fine process is used, the current consumption is about several ten mA, and therefore, there is enough room for improvement.
In addition, the CMOS-inverter-type frequency divider circuit has a characteristic that a free-running frequency (maximum operation frequency) differs by as much as about ±50% depending on variations in threshold voltages due to the individual differences of MOS transistors. In order to cope with such a characteristic, it is necessary to set a large design margin so that a frequency divider circuit normally operates even if the free-running frequency of the frequency divider circuit is no more than −50% of an average free-running frequency. However, in this case, a current considerably larger than an average current flows, and the average of the free-running frequency becomes considerably larger than the average of an operation frequency that are originally needed. As a result, unnecessary large currents flow in most of frequency divider circuits, and power is consumed wastefully.
Meanwhile, one of recent papers has reported a CMOS-inverter-type frequency divider circuit having a VT0 correction function of detecting variations in threshold voltages (VT0) due to the individual differences of MOS transistors, and correcting variations in free-running frequencies (see Non-Patent Literature 3, FIG. 5 (VT0 detection circuit)).
FIG. 8 is a diagram showing the comparison among the features of the ECL-type frequency divider circuit, the first CMOS-inverter-type frequency divider circuit, and the second CMOS-inverter-type frequency divider circuit having the VT0 correction function.